This is regarding a job opening with Juniper Network, Raza Microelectronics, Cortina Systems (all in Bangalore), and Ikoa Hyderabad @ their Bangalore facilities.
Location:
Requirement 1: Lead ASIC Verification Engineer
Details:
- 6-10 yrs Lead verification team to successfully complete block/chip/system level verification.
- Perform ASIC verification for large, complex high-speed ASICs for Juniper's next generation of networking products.
- Develop detailed test plans, block and system-level test benches and verification environments, achieve complete coverage to ensure first working silicon.
- Develop functional models for System level architectural validation.
- Lead ASIC and system bring-up. Lead a team of engineers to successfully deliver chip from specification to tape out.
- Need to make and maintain schedule. Develop modeling/verification/coverage methodology.
- You will work closely with logic designers & software developers.
Requirement 2: Lead ASIC Design Engineer
Details:
- 6 -8 yrs Lead design team to successfully complete block level/full chip design.
- Develop architecture, micro-architecture and RTL implementation for ASIC's and systems for high-performance networking products.
- Work with verification engineers to ensure first-time working silicon. Perform logic synthesis and timing analysis.
- Lead a team of engineers to successfully deliver chip from specification to tapeout.
- Work with physical design and signal integrity teams to achieve timing closure in routed netlists.
- Need to make and maintain schedule.
Requirement 3: ASIC Verification Engineer
Details:
- 5-7 yrs Responsible for block level / full chip verification.
- Perform ASIC verification for large, complex high-speed ASICs for Juniper's next generation of networking products.
- Develop detailed test plans, block and system-level test benches and verification environments, achieve complete coverage to ensure first working silicon.
- Develop functional models for System level architectural validation.
- Assist in ASIC and system bring-up. You will work closely with logic designers, software developers.
Requirement 4: ASIC Design Engineer
Details:
- 4 -6 yrs Responsible for block level / full chip design.
- Develop micro-architecture and RTL implementation for ASIC's and systems for high-performance networking products.
- Work with verification engineers to ensure first-time working silicon.
- Perform logic synthesis and timing analysis.
- Work with physical design and signal integrity teams to achieve timing closure in routed netlists.
Requirement 5: ASIC Design Engineer
Details:
- 2 -5 yrs Responsible for block level design.
- Develop micro-architecture and RTL implementation for ASIC's and systems for high-performance networking products.
- Work with verification engineers to ensure first-time working silicon. Perform logic synthesis and timing analysis.
Requirement 6: ASIC Verification Engineer
Details:
- 2+yrs Responsible for block level verification.
- Perform ASIC verification for large, complex high-speed ASICs for Juniper's next generation of networking products.
- Develop detailed test plans, block-level test benches and verification environments; achieve complete coverage to ensure first working silicon.
- You will work closely with logic designers.
Desired skills for “Verification' Leads”:
Education & Experience:
- B.E / B. Tech / MS / M. Tech. - EE / CS with 5+ years experience
Skill sets:
- Very good knowledge and hands-on experience in C++/Vera/Specman and System Verilog
- Hands on experience in test bench development for Multi-Million Gate ASICs
- Detailed test plan generation and implementation
- Good knowledge in verification of CPU
- Hands on experience in scripting, debugging, automation, bug tracking, batch jobs, etc..
- Good Knowledge in Ethernet Protocols is a plus
- Detailed knowledge of CPU internals is a plus
Desired skills for “ASIC Design Engineer”
RTL development, Understanding of the spec for low power design, ownership of sub modules, integration activities, RTL Debug, Netlist debug.
Education & Experience:
- BE / B. Tech, ME / MS / M. Tech with 2-8 years experience
Skill sets:
- Vera / Specman / System Verilog / High Speed ASIC Design / Low power Designs / RTL
- Logic Design & RTL Implementation (Verilog/VHDL)
- Functional Verification (Vera/Specman/ System Verilog)
- Experience in high speed and multi-million gate, ASIC/SoC designs.
- Architecture and micro-architecture design of the ASICs, RTL design and synthesis, Logic and Timing
- Synthesis
- RTL debug skills
- Experience on low power designs will be an added advantage.
- Design for Test will be an advantage
- Exposure to Logic Synthesis (DC), Static Timing Analysis
APPLY: If interested, send your updated resume in word format to ms at techpointsolutions dot com along with following details:
- Job you’re applying for:
- Current CTC:
- Expected CTC:
- Notice Period: